Title :
A configurable multiprocessor and dynamic load balancing for parallel LU factorization
Author :
Wang, Xiaofang ; Ziavras, Sotirios G.
Author_Institution :
Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA
Abstract :
Summary form only given. The exponentially increasing complexity of many scientific applications and the high cost of supercomputing force us to explore new, sustainable, and affordable high-performance computing platforms. Recent significant advances in FPGA technology and the inherent advantages of configurable logic have brought about new research efforts in the configurable computing field: parallel processing on configurable chips. We explore here parallel LU factorization of large sparse block-diagonal-bordered (BDB) matrices on a configurable multiprocessor that we have designed and implemented. A dynamic load balancing strategy is proposed and analyzed. Performance results for IEEE power test systems are provided. Our research provides evidence that configurable logic can be a viable alternative to high-performance scientific computing.
Keywords :
matrix decomposition; multiprocessing systems; parallel processing; resource allocation; sparse matrices; FPGA technology; IEEE power test system; configurable chip; configurable logic; configurable multiprocessor; dynamic load balancing; high-performance scientific computing; parallel LU factorization; parallel processing; sparse block-diagonal-bordered matrix; Concurrent computing; Costs; Equations; Field programmable gate arrays; Load management; Logic; Parallel processing; Scientific computing; Sparse matrices; Supercomputers;
Conference_Titel :
Parallel and Distributed Processing Symposium, 2004. Proceedings. 18th International
Print_ISBN :
0-7695-2132-0
DOI :
10.1109/IPDPS.2004.1303282
