Title :
Low power image processing using MuCCRA-3: A Dynamically Reconfigurable Processor Array
Author :
Kimura, Masayuki ; Saito, Yoshiki ; Sano, Toru ; Kato, Masaru ; Tunbunheng, Vasutan ; Yasuda, Yoshihiro ; Amano, Hideharu
Author_Institution :
Dept. of Inf. & Comput. Sci., Keio Univ., Yokohama, Japan
Abstract :
A kind of image processing with a low power dynamically reconfigurable processor array (DRPA) prototype MuCCRA-3 implemented with 65 nm CMOS process will be shown. The measured power is also exhibited during execution, and compared with Xilinx Virtex-5 FPGA using exactly the same environment. The demonstration shows that more than 10 times better power efficient computation is achieved using MuCCRA-3. The application design environment of MuCCRA-3 is also shown.
Keywords :
CMOS integrated circuits; field programmable gate arrays; image processing; low-power electronics; microprocessor chips; reconfigurable architectures; CMOS process; MuCCRA-3; Xilinx Virtex-5 FPGA; design environment; dynamically reconfigurable processor array prototype; low power image processing; power efficient computation; CMOS process; Clocks; Computer science; Energy consumption; Field programmable gate arrays; Image processing; Manipulator dynamics; Power measurement; Prototypes; Switches;
Conference_Titel :
Field-Programmable Technology, 2009. FPT 2009. International Conference on
Conference_Location :
Sydney, NSW
Print_ISBN :
978-1-4244-4375-8
Electronic_ISBN :
978-1-4244-4377-2
DOI :
10.1109/FPT.2009.5377614
