3-tier reconfiguration model For FPGAs using Hardwired Network on Chip

We envision that future field-programmable gate arrays (FPGAs) will use a hardwired network on chip (HWNoC) as a unified interconnect for functional communications (data and control) as well as configuration (bitstream for soft IPs). In this paper we present a 3-tier reconfiguration model that uses the HWNoC as the underlying platform to realize dynamic loading, starting, and stopping of applications. The model ensures that applications are guaranteed their required resources (LUTs, communication, memory). Resource allocation is performed globally at design time. Applications are started and stopped dynamically at run time, yet are composable, i.e. do not affect each other when they do so. Our model comprises three layers: system manager, application manager, and application. The system manager instantiates (configures) and enforces the resource allocation (LUTs, NoC connections, memories) at run time. Each application is independent, and is accompanied by an application manager that programs (starts and stops) the application, within its allocated resources (a virtual platform). We model our system in cycle-accurate transaction-level SystemC which includes bitstream loading, HWNoC and IP programming, clocking, reset, computation.