DVFLEX: a flexible MPEG real time video codec

The MPEG-2 video coding standard offers great latitude in implementation and covers a wide variety of applications. The DVFLEX video encoder allows one to take advantage of this flexibility by making the whole coding loop including the bitstream generation, software programmable. The DVFLEX architecture is basically an array of linearly-connected processing modules. These modules are based on the MVP (TMS320C80) and include dedicated I/O ports for video, bitstream and inter-processor communications. All these I/O ports allow the processing to be performed in parallel with I/Os. The processing workload is distributed among these modules on an image region per processor basis. As for the on-chip MVP processors, tasks assignment is much more constrained because of the bitstream handling problems. Although suboptimal, the solution we describe is simple and gives satisfactory results. However, the on-chip to off-chip memory I/Os have to be carefully handled so as to keep the processors busy