The effect of node size, heterogeneity, and network size on FPGA based NoCs

Modern FPGAs are used to implement complex Systems-on-Chip (SoCs) and more recently Networks-on-Chip (NoCs). NoCs consist of computing nodes that are connected via switches or routers to a network of point-to-point links that define the topology. Previous work has investigated appropriate topology choices for ASICs as dictated by their electrical characteristics. However, since a FPGA has a prefabricated interconnect, their NoC implementations are not restricted by these concerns. Preliminary work has looked at homogeneous multiprocessor networks-on-chip on FPGAs and suggests that these systems perform differently on FPGAs than ASICs. In this work, we looked at the effects of the number of nodes, node sizes and heterogeneity on NoC performance. Assuming that the network node is not the critical path, we found that NoC performance is only dependent on the number of nodes and is not impacted by the node size or heterogeneity of nodes.