Modelling degradation in FPGA lookup tables

Reliability is an issue which is becoming increasingly important in the VLSI world, and FPGAs are no exception. FPGAs have the potential to support novel reliability-enhancement schemes and to develop these it is crucial to understand how degradation mechanisms affect basic soft-logic resources. In this work, a reliability model for an FPGA lookup table (LUT) is developed, covering three important ageing effects. It is demonstrated how the model can be used to analyse the onset of degradation and assess the residual functionality of damaged resources.