Title :
A VLSI architecture for real time code book generator and encoder of a vector quantizer
Author :
Brahmbhatt, Apurva
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Abstract :
The current vector quantizer (VQ) hardware employs static instead of dynamic code book generation as the latter demands intensive computation and corresponding expensive hardware, even though it offers better image quality. This paper proposes a VLSI architecture for a real-time code book generator and encoder of 512×512 images at 30 frames/s. The resulting design consists of a single VQ processor and an image buffer memory chip, if implemented using 0.8 μm CMOS technology
Keywords :
CMOS memory circuits; VLSI; buffer storage; decoding; digital signal processing chips; image coding; vector quantisation; 0.8 micron; CMOS technology; VLSI architecture; VQ hardware; decoding; image buffer memory chip; image quality; real time code book generator; real time encoder; static code book generation; vector quantizer; Books; Clustering algorithms; Computer architecture; Encoding; Hardware; Image coding; Neurons; Pixel; Space technology; Very large scale integration;
Conference_Titel :
Image Processing, 1996. Proceedings., International Conference on
Conference_Location :
Lausanne
Print_ISBN :
0-7803-3259-8
DOI :
10.1109/ICIP.1996.561072
