• DocumentCode
    3048606
  • Title

    An optimal scheduling method for parallel processing system of array architecture

  • Author

    Ito, Kazuhito ; Iwata, Tadashi ; Kunieda, Hiroaki

  • Author_Institution
    Dept. of Electr. & Electr. Syst., Saitama Univ., Urawa, Japan
  • fYear
    1997
  • fDate
    28-31 Jan 1997
  • Firstpage
    447
  • Lastpage
    454
  • Abstract
    In high-level synthesis for digital signal processing systems of array structured architecture, one of the most important procedures is the scheduling. By taking into account the allocation of operations to processors, it is mandatory to take into account the communication time between processors. In this paper we propose a scheduling method which derives an optimal schedule achieving the minimum iteration period and latency for a given signal processing algorithm on the specified processor array. The scheduling problem is modeled as an integer linear programming and solved by an ILP solver. Furthermore, we improve the scheduling method so that it can be applied to large scale signal processing algorithms without degrading the schedule optimality
  • Keywords
    cellular arrays; high level synthesis; parallel architectures; scheduling; ILP solver; array architecture; array structured architecture; digital signal processing systems; high-level synthesis; optimal scheduling; parallel processing; scheduling; Degradation; Delay; Digital signal processing; High level synthesis; Integer linear programming; Large-scale systems; Optimal scheduling; Parallel processing; Processor scheduling; Signal processing algorithms;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 1997. Proceedings of the ASP-DAC '97 Asia and South Pacific
  • Conference_Location
    Chiba
  • Print_ISBN
    0-7803-3662-3
  • Type

    conf

  • DOI
    10.1109/ASPDAC.1997.600300
  • Filename
    600300