Scalable VLSI architectures for full-search block matching algorithms

Author

Yeh, Yuan-Hau ; Lee, Chen-Yi

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

1

fYear

1996

fDate

16-19 Sep 1996

Firstpage

1035

Abstract

This paper presents two VLSI architectures for full search block matching motion estimation (ME) algorithm based on overlapped search data flow. The proposed VLSI architectures have three specific features: (1) they contain a processor element (PE) array which provides sufficient computational power and achieves 100% hardware efficiency; (2) they contain stream memory banks which provide scheduled data flow requested by PE for computing mean absolute distortion (MAD); and (3) they both have minimum memory bandwidth to save I/O pin-count

Keywords

VLSI; data flow computing; digital signal processing chips; image matching; motion estimation; parallel algorithms; parallel architectures; search problems; video coding; I/O pin-count; digital video services; full-search block matching algorithms; hardware efficiency; mean absolute distortion; minimum memory bandwidth; motion estimation algorithm; overlapped search data flow; processor element array; scalable VLSI architectures; scheduled data flow; stream memory banks; video coding; Bandwidth; Computer architecture; Data engineering; Data flow computing; Encoding; Hardware; Motion estimation; Niobium; Streaming media; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Image Processing, 1996. Proceedings., International Conference on

Conference_Location

Lausanne

Print_ISBN

0-7803-3259-8

Type

conf

DOI

10.1109/ICIP.1996.561084

Filename

561084