An on-line testable UART implemented using IFIS

This paper presents the design of a complex integrated circuit realised through a novel on-line test methodology. The circuit and its exact conventional equivalent both have been realised in FPGA technology. As such it represents one of the more complex designs realised to date using on-line test approaches. The approach used IFIS (If it Fails It Stops) incorporates dual-rail coding of individual data and a handshaking protocol, which substantially simplifies the detection of failure. Details of the IFIS methodology are given. The IFIS and conventional re-design of a commercial UART are reported, focusing on methodological issues as well as size and speed. Output traces are shown for the IFIS UART on FPGA operating under fault-free conditions and with deliberate failures injected