Area, delay, power, and cost trends for metal-programmable structured ASICs (MPSAs)

As integrated circuits are scaled to finer process geometries, the risk involved with the increased design effort and high NRE costs becomes too great for some applications. FPGAs offer one solution, but for high performance, high volume, or low power applications, FPGAs may not be suitable. For some of these applications, structured ASICs may provide a better solution. Structured ASICs share many of the same characteristics as FPGAs, but consume less power, are more dense, and can run faster. Despite these advantages, structured ASICs have not yet achieved the level of popularity some had predicted. There are several possible reasons, including unfamiliar technology, immature CAD, and claimed advantages which have not yet been concretely demonstrated. In much the same way that it has helped improve FPGA adoption, we believe that an increased public research effort can begin to address many of these issues. This paper takes a step in this direction by investigating metal-programmable structured ASICs, or MPSAs. We determine the area, delay, and power trends and quantify the cost advantages of MPSAs relative to cell based ICs (CBICs) for a wide range of possible MPSA logic architectures and layout assumptions. In particular, we quantify the impact of the number of user-defined metal mask layers on these metrics. Results suggest the number of these programmable layers should be as small as possible for most MPSAs, unless very large die sizes are required.