American option pricing on reconfigurable hardware using Least-Squares Monte Carlo method

The valuation of optimal exercise of American-style options is one of the most important problems in option pricing theory. Unlike European options, American options have the feature of early exercise, which makes it hard to simulate using the simple Monte Carlo method. A number of extended Monte Carlo methods have been published recently; the Least-Squares Monte Carlo (LSMC) suggested by Longstaff and Schwartz is one of the most adopted algorithms in the industry. Although hardware acceleration technique has been used in financial computing for several years, there has not been any published hardware implementation of the LSMC method. In this paper, we present an FPGA hardware architecture for the acceleration of the LSMC method. In it, the Quasi-Monte Carlo method is adopted for stock price paths generation. Our real FPGA hardware implementation on a Xilinx Virtex-4 XC4VSX55 chip achieves 25x and 18x speed-ups in the Monte Carlo simulation and regression steps of the American option pricing, respectively, compared to an equivalent pure software implementation captured in C++ and run on an Intel Xeon 2.8 GHz CPU. This results in an overall speed-up figure of 20x compared to a CPU-based implementation. Given that the FPGA implementation is clocked at only 75MHz, the FPGA implementation also exhibits considerable energy savings.