A parallel spiking neural network simulator

Author

Cheung, Kit ; Schultz, Simon R. ; Leong, Philip H W

Author_Institution

Dept. of Comput. Sci. & Eng., Chinese Univ. of Hong Kong, Hong Kong, China

fYear

2009

fDate

9-11 Dec. 2009

Firstpage

247

Lastpage

254

Abstract

An FPGA-based systolic architecture for the high speed simulation of spiking neural networks is presented. The design is an implementation of Izhikevich´s neuron model and employs optimizations for the typical case where neuron activity is low. Since execution time required is related to the activity level, performance of the design can be improved by an order of magnitude.

Keywords

field programmable gate arrays; neural nets; systolic arrays; FPGA-based systolic architecture; neuron model; parallel spiking neural network simulator; Biological neural networks; Biological system modeling; Brain modeling; Computational modeling; Computer simulation; Field programmable gate arrays; Frequency; Large-scale systems; Neural networks; Neurons;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Technology, 2009. FPT 2009. International Conference on

Conference_Location

Sydney, NSW

Print_ISBN

978-1-4244-4375-8

Electronic_ISBN

978-1-4244-4377-2

Type

conf

DOI

10.1109/FPT.2009.5377667

Filename

5377667

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3049140