A parallel architecture of AdaBoost-based face detection for gaze estimation

Face detection is an essential application in image processing and computer vision. In this paper, a parallel architecture for AdaBoost algorithm is proposed to support face detection in the embedded system. Some optimizations for the AdaBoost algorithm are applied to accelerate the process. Based on the software/hardware co-design methodology, a configurable high performance CPU (Nios) can take charge of task scheduling, image scaling and simple processing. Dedicated hardware accelerators are designed to deal with data intensive computing tasks through multi-level parallelism to meet the real-time requirement in embedded applications. The architecture is prototyped on Altera Cyclone II FPGA The evaluation result shows that the system performs real-time detection with low resource consumption and high detection rate (96.7%). The detection speed of image consisting 640 × 480 pixels is 12 frames/s, and 41 frames/s for image consisting 320 × 240 pixels. It meets the requirement of gaze estimation.