Title :
Concurrent error detection/correction in the HAL MMU chip
Author :
Chang, David Chih-Wei ; Saxena, Nirmal R.
Author_Institution :
HAL Comput. Syst., Campbell, CA, USA
Abstract :
The authors describe three concurrent error detection and correction methods used in various address translation tables in the HAL Memory Management Unit (MMU). Virtually indexed and virtually tagged cache architecture is exploited to provide an almost fault-secure hardware coherence mechanism in MMU. Low overhead linear polynomial codes have been chosen in these designs to minimize both the hardware and software instrumentation impact.
Keywords :
fault tolerant computing; HAL memory management unit; address translation tables; cache architecture; concurrent error correction; concurrent error detection; fault-secure hardware coherence mechanism; linear polynomial codes; software instrumentation impact; Collaborative software; Computer architecture; Computer errors; Concurrent computing; Delay; Error correction; Error correction codes; Hardware; Instruments; Memory management;
Conference_Titel :
Fault-Tolerant Computing, 1993. FTCS-23. Digest of Papers., The Twenty-Third International Symposium on
Conference_Location :
Toulouse, France
Print_ISBN :
0-8186-3680-7
DOI :
10.1109/FTCS.1993.627366
