Concurrent error detection/correction in the HAL MMU chip

Author

Chang, David Chih-Wei ; Saxena, Nirmal R.

Author_Institution

HAL Comput. Syst., Campbell, CA, USA

fYear

1993

fDate

22-24 June 1993

Firstpage

630

Lastpage

635

Abstract

The authors describe three concurrent error detection and correction methods used in various address translation tables in the HAL Memory Management Unit (MMU). Virtually indexed and virtually tagged cache architecture is exploited to provide an almost fault-secure hardware coherence mechanism in MMU. Low overhead linear polynomial codes have been chosen in these designs to minimize both the hardware and software instrumentation impact.

Keywords

fault tolerant computing; HAL memory management unit; address translation tables; cache architecture; concurrent error correction; concurrent error detection; fault-secure hardware coherence mechanism; linear polynomial codes; software instrumentation impact; Collaborative software; Computer architecture; Computer errors; Concurrent computing; Delay; Error correction; Error correction codes; Hardware; Instruments; Memory management;

fLanguage

English

Publisher

ieee

Conference_Titel

Fault-Tolerant Computing, 1993. FTCS-23. Digest of Papers., The Twenty-Third International Symposium on

Conference_Location

Toulouse, France

ISSN

0731-3071

Print_ISBN

0-8186-3680-7

Type

conf

DOI

10.1109/FTCS.1993.627366

Filename

627366

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3050185