DocumentCode :
3050194
Title :
Use of protocol validation and verification techniques in the design of a fault-tolerant computer architecture
Author :
Shambroom, W. David
Author_Institution :
Charles River Data Syst., Inc., Arlington, TX, USA
fYear :
1993
fDate :
22-24 June 1993
Firstpage :
636
Lastpage :
640
Abstract :
A fault-tolerant computer architecture has been designed to meet the requirements of applications which require high system availability but can tolerate a short recovery time (limited to a few minutes) in the event of component failure. Critical to the success of this architecture is a heartbeat protocol governing communication between two independent processor subsystems. This protocol, which ensures correct negotiation of a primary/secondary relationship between the two subsystems in the presence of any combination of component failures, has been specified using a finite-state-machine description. The author describes the protocol specification and its validation (for formal correctness) and verification (for functional correctness) using the technique of computerized exhaustive exploration of global system state space.
Keywords :
protocols; component failure; fault-tolerant computer architecture; finite-state-machine; formal correctness; functional correctness; heartbeat protocol; high system availability; protocol specification; protocol validation; protocol verification; Application software; Availability; Computer architecture; Data systems; Fault tolerance; Fault tolerant systems; Hardware; Heart beat; Protocols; Rivers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Fault-Tolerant Computing, 1993. FTCS-23. Digest of Papers., The Twenty-Third International Symposium on
Conference_Location :
Toulouse, France
ISSN :
0731-3071
Print_ISBN :
0-8186-3680-7
Type :
conf
DOI :
10.1109/FTCS.1993.627367
Filename :
627367
Link To Document :
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