Design of an ASIC for fast signal recognition and code acquisition in DS-SS-CDMA receivers

This paper deals with the design and realization of an application specific integrated circuit (ASIC) for fast signal recognition and code acquisition (SR/CA) in direct-sequence spread-spectrum code division multiple access (DS-SS-CDMA) receivers operating in a satellite or terrestrial radio network. The SR/CA problem is often the bottleneck of any DS-SS-CDMA system operating in spread-ALOHA random access mode for the common access channel or when packet mode operation is envisaged. The single ASIC implementation provides a reliable, high-performance, low-cost, low-power consumption solution to such a problem. In particular, this paper explains how a parallel acquisition circuit can be effectively implemented on a single chip with a 1.0 μm CMOS (complementary metal oxide silicon) technology, complying with the specifications of the ESA (European Space Agency)/Inisel Ku-band CDMA VSAT (very small aperture terminal) system