DocumentCode :
3050385
Title :
Automatic generation of test vectors for SCR-style specifications
Author :
Blackburn, Mark R. ; Busser, Robert D. ; Fontaine, Joseph S.
Author_Institution :
Software Productivity Consortium, Herndon, VA, USA
fYear :
1997
fDate :
16-19 Jun 1997
Firstpage :
54
Lastpage :
67
Abstract :
This paper provides the basis for integrating the Software Cost Reduction (SCR) specification method with the T-VEC (Test VECtor) test vector generator and specification analysis system. The SCR model is mapped to the T-VEC model to support automatic test vector generation for SCR specifications. The T-VEC system generated test vectors for an example SCR specification that was translated into the T-VEC language. The relationships between the models and the resulting test vectors are described. Two general guidelines for the translation process were identified that are fundamental for testing specifications that use event operators and for structuring the specifications to provide tests for all specified requirements
Keywords :
program testing; program verification; SCR-style specifications; Software Cost Reduction; T-VEC; event operators; specification method; test vector generator; test vectors; Automatic testing; Certification; Costs; FAA; Guidelines; Packaging; Productivity; Software testing; System testing; Thyristors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Assurance, 1997. COMPASS '97. Are We Making Progress Towards Computer Assurance? Proceedings of the 12th Annual Conference on
Conference_Location :
Gaithersburg, MD
Print_ISBN :
0-7803-3979-7
Type :
conf
DOI :
10.1109/CMPASS.1997.613225
Filename :
613225
Link To Document :
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