Analysis of current sharing and controller design fundamental for paralleled DC/DC power converters

The key technology for multi power converters paralleled is active current sharing. In this paper, out loop current sharing scheme is used as an example to investigate the relationship between output impedance and current balance. It is induced that the deviation of output impedance is the essential reason that degrades the performance of current sharing, and the bandwidth of current sharing loop must exceed the frequency area where exist obvious output impedance deviation to obtain perfect current sharing. Simulation results validate the proposed analysis and design method.