Analysis of power in dynamic comparators

The need for ultra low-power, area efficient and high speed analog-to-digital converters (ADCs) is pushing towards the use of dynamic comparators to maximize speed, power efficiency and re-configurability. In this paper an analysis on the power of the dynamic comparators will be presented and analytical expressions are derived. From the analytical expressions, designers can obtain an intuition about the main contributors to the comparator power consumption and also fully explore the tradeoffs in dynamic comparator design such as offset voltage, power and speed. To validate the analytical expressions, the power is first derived analytically and then will be compared to the result of simulating a conventional dynamic comparator in 0.18μm CMOS. A good agreement between these two verifies the effectiveness of the presented analysis.