Title :
Advanced multiple-step resist etchback planarization
Author :
de Bruin, L. ; van Laarhoven, J.M.F.G.
Author_Institution :
Philips Res. Lab., Eindhoven, Netherlands
Abstract :
Loading effects during resist etchback (REB) planarization result in incomplete planarization when multiple levels have to be planarized. The reason is that the ratio of oxide to resist areas, which are exposed to the plasma, changes as the etchback proceeds. This causes a change in etch selectivity, because the resist etch rate is strongly dependent on the oxide/resist area ratio. A multiple-step planarization process has been developed to minimize the influence of the loading effects on the final topology. During etchback, the CO-emission signal is traced. After observing a typical change in the CO-emission, the plasma conditions of the etch process are modified by decreasing the oxygen flow-rate in such a way that the etch selectivity of oxide/resist is kept constant. This multiple-step REB planarization process was used successfully in a 0.7- mu m CMOS process to produce a 1-Mb SRAM the surface topology was reduced to less than 0.1 mu m.<>
Keywords :
CMOS integrated circuits; integrated circuit technology; metallisation; resists; sputter etching; surface topography; 0.7 micron; 1 Mbit; CMOS process; O/sub 2/ flow rate; SRAM; etch selectivity; loading effects; multiple levels; multiple-step resist etchback planarization; oxide to resist area ratio; plasma etching; resist etch rate; surface topology; topology; Etching; Laboratories; Planarization; Plasma applications; Plasma measurements; Production; Random access memory; Resists; Thickness measurement; Topology;
Conference_Titel :
VLSI Multilevel Interconnection Conference, 1988. Proceedings., Fifth International IEEE
Conference_Location :
Santa Clara, CA, USA
DOI :
10.1109/VMIC.1988.14219
