A new high-resolution and high-speed open-loop CMOS sample and hold circuit

A new open loop, high resolution CMOS sample and hold (S/H) circuit is presented in this article. This structure is designed based on a new method in order to decrease dependency of the storing charge of holding capacitors to the charge injection of transistors. It is constructed of dummy switches and auxiliary capacitor to decrease the voltage spikes that are produced during the sampling mode. Due to the high linearity feature of our proposed design in comparison with previous works, it has been reached to a great improvement in signal to noise ratio (SNR) up to about 15dB. Also, its ENOB have been increased to 16 bits. Another advantages of our proposed design are its lower power dissipation and its high input voltage range. Also the optimum functionality of our proposed circuit does not damaged by the process variations in different corners. As our proposed S/H circuit has been designed in open loop structure, it is suitable for high speed applications.