A methodolgy for characterizing cell testability

There is an increasing amount of effort spent in designing integrated circuits to be more testable in hopes of increasing quality levels. Most of this effort has focused on modifying the schematic-level design of circuits to improve their stuck-at fault coverage. However, many researchers have shown that a circuit´s stuck-at fault coverage is not an accurate predictor of IC quality for low values of DPM. This work focuses on improving the testability of cells at the level of abstraction that directly interacts with the manufacturing defects - the physical design level. We first define a metric for measuring the effective testability of a cell. The effective testability of a cell is based on the physical design of the cell, the circuit in which the cell is used, and the methods that will be used to test the circuit. In this paper the term testability refers to effective testability. We then show how this metric is used to guide cell design for testability