A new technique for background calibration of pipelined ADCs

Author

Mohammadi, M. ; Alipour, Anahita ; Aghdam, Esmaeil Najafi ; Sadeghipour, Khosrov D.

Author_Institution

Sahand Univ. of Technol., Tabriz, Iran

fYear

2013

fDate

14-16 May 2013

Firstpage

1

Lastpage

5

Abstract

This paper presents a new background calibration technique for pipelined ADCs by means of slow high accurate ADC (SHADC). Errors due to finite and nonlinear gain of inter-stage operational amplifier are calibrated. Correction coefficients are estimated by using the well-known LMS algorithm. Obtained results from simulation of a 13bit 1.5bit/stage pipelined ADC behavioral model reveals the effectiveness of the proposed technique to calibrate the mentioned errors. The ADC achieves a DNL of -0.8 LSB from -47.03 LSB, an INL of 2.84 LSB from 66.48 LSB and SNDR of 73.55 dB from 40.64 dB after calibration.

Keywords

analogue-digital conversion; calibration; least mean squares methods; operational amplifiers; LMS algorithm; SHADC; analog-to-digital converters; background calibration technique; correction coefficients; finite gain; interstage operational amplifier; nonlinear gain; pipelined ADC behavioral model; slow high accurate ADC; word length 13 bit; CMOS integrated circuits; Calibration; Flowcharts; Gain; Least squares approximations; Simulation; Switches; LMS algorithm; background calibration; pipelined ADC;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Engineering (ICEE), 2013 21st Iranian Conference on

Conference_Location

Mashhad

Type

conf

DOI

10.1109/IranianCEE.2013.6599864

Filename

6599864