Title :
Low power design of successive approximation registers
Author_Institution :
ECE Dept., Worcester Polytech. Inst., Worcester, MA, USA
Abstract :
This paper presents low power design methods for successive approximation registers (SARs) that may serve as the digital part of a successive approximation analog to digital converter (SA-ADC). The SAR is designed in 130nm technology in the sub-threshold region to meet the goal of reduced power consumption.
Keywords :
analogue-digital conversion; logic design; low-power electronics; shift registers; SA-ADC; SAR; analog to digital converter; low power design methods; size 130 nm; subthreshold region; successive approximation registers; Approximation methods; Clocks; Logic gates; Power demand; Shift registers; Threshold voltage; Analog to Digital Converter; Clock; Dynamic Register; Static Register;
Conference_Titel :
Electrical Engineering (ICEE), 2013 21st Iranian Conference on
Conference_Location :
Mashhad
DOI :
10.1109/IranianCEE.2013.6599867
