Enhancement of parallelism for tearing-based circuit simulation

A new circuit simulation system is presented with techniques “Subcircuit Balancing with Estimated Update operation count” (SBEU) and “Asynchronous Distributed Row-based interconnection parallelization” (A-DR). SBEU estimates Gaussian elimination cost of each subcircuit by counting number of update operations to achieve balanced circuit partitioning. A-DR makes it possible to overlap numerical operations and interprocessor communications in parallel Gaussian elimination of interconnection equations. On a 16-PE distributed memory parallel machine, an experimental simulation shows 9.9 times speedup over 1PE and distribution of the time consumed for each subcircuit is within ±26% deviation from the median