Memory architecture of a video-rate image convolver

This paper describes the design of an image convolver suitable for the convolution of a (256 × 256) image with large filter impulse responses in under 1/30 of a second. The memory architecture of the convolver is based on the structures associated with parallel and pipelined FFT/NTT processors that use ROM oriented implementation of the Residue Number System and a 2 D radix-r Ordered-input, Ordered-output FFT algorithm. The 2 D convolution operation is performed by the use of overlap-save technique of sectioned convolutions.