A New Design Method for VLSI Signal Processors

This paper presents a new method of designing digital signal processors for very large scale integrated (VLSI) circuit implementation with residue number systems (RNS), as opposed to the binary number systems traditionally used. In an RNS, a number is represented by its residues, modulo a set of relatively prime integers. The basic operations of modulo addition and multiplication are simpler in RNS because they can be executed independently in each residue class. Consequently, a desired linear function can be executed in a set of parallel channels on a chip, where each channel performs the same calculation modulo the integer used in that channel. Complexity is thus reduced by two mechanisms. Interconnections between parallel channels are eliminated and all operations are performed modulo the small integer used in each parallel channel of the RNS structure. The square law of circuit complexity applied to this set of small integers results in small, simple circuits. Speed of computation is increased because carry propagation delays are avoided. Further, the RNS design is combined with systolic arrays in such a way that the desired function becomes a parallel set of nearest neighbor-connected identical cells, each of which is minimally complex. The regularity minimizes interconnections and design time -- only one master VLSI macrocell that can be optimized and replicated under computer-aided design (CAD) control is needed.