Title :
VLSI Reed Solomon Decoder Design
Author :
Maki, Gary K. ; Owsley, Patrick A. ; Cameron, Kelly B. ; Venbrux, Jack
Author_Institution :
Microelectronics Research Center, College of Engineering, University of Idaho, Moscow, Idaho 83843
Abstract :
A Reed Solomon code is a highly efficient error correcting code that NASA will use in future space communication missions. A VLSI implementation of the decoder is presented that accepts data rates of 80Mbits/second. A total of 7 chips are needed and operate with the symbol clock being the system clock for the chip set. Approximately 1.65 billion Galois Field operations per second are achieved with this chip set.
Keywords :
Clocks; Decoding; Error correction codes; Galois fields; Lifting equipment; NASA; Polynomials; Reed-Solomon codes; Systolic arrays; Very large scale integration;
Conference_Titel :
Military Communications Conference - Communications-Computers: Teamed for the 90's, 1986. MILCOM 1986. IEEE
DOI :
10.1109/MILCOM.1986.4805860
