An Ultra High Speed Optoelectronic Multiplexer Bus as an Integral Design Component for a Parallel Computer

As opposed to communication buses that connect a computer to its external environment, this paper proposes a parallel computer architecture that integrates an ultra high speed communication bus as part on the computer´s internal data transfer. The architecture proposed has potential application in the class of problems which may be processed using perfect shuffle algorithms. It does however, lend itself to other applications since in effect the ultra high speed serial bus replaces a comprehensive crossbar interconnection switch. An example of the architecture as applied to the Fast Fourier Transform is given, and a method of determining computer design parameters to accomplish the application is also given.