Fixed Point Implementation of Cross Coupled Phase Lock Loops

A cross coupled phase lock loop (CCPLL) represents a novel technique for separating and tracking a wide variety of signals in the presence of an interfering source. In this paper, we examine the tracking performance of CCPLL systems when implemented in fixed point arithmetic. A summary of results stemming from an extensive computer aided analysis is presented which clearly illustrates system performance as a function of the number of bits utilized to represent various system variables. Some analytical results governing the performance of the CCPLL in a fixed point implementation are also provided. These results are useful in providing a guideline for fixed point digital CCPLL designs.