DocumentCode
3052373
Title
Bare die test
Author
Parker, Robert H.
Author_Institution
Inf. Sci. Inst., Univ. of Southern California, Marina del Rey, CA, USA
fYear
1992
fDate
18-20 Mar 1992
Firstpage
24
Lastpage
27
Abstract
The author describes a bare die test approach that uses a temporary interconnect technique overlaid on a reconstructed pseudo-wafer of individual bare dice. This overlay technique maps design-specific pad locations to a standard grid that can be tested with a universal membrane probe. The proposed approach allows the development cost of a thin-film membrane probe to be shared across many die types, thus reducing the cost and complexity of tooling new die types. An experiment performed to validate this approach is described
Keywords
hybrid integrated circuits; integrated circuit testing; modules; probes; production testing; bare die test approach; design-specific pad locations; multichip modules; reconstructed pseudo-wafer; standard grid; temporary interconnect technique overlaid; thin-film membrane probe; universal membrane probe; Biomembranes; Circuit testing; Costs; Foundries; Integrated circuit interconnections; Integrated circuit packaging; Laboratories; Probes; Thin film circuits; Wafer scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Multi-Chip Module Conference, 1992. MCMC-92, Proceedings 1992 IEEE
Conference_Location
Santa Cruz, CA
Print_ISBN
0-8186-2725-5
Type
conf
DOI
10.1109/MCMC.1992.201438
Filename
201438
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