DocumentCode :
3052609
Title :
Cool Mega-Array: A highly energy efficient reconfigurable accelerator
Author :
Ozaki, N. ; Yoshihiro, Y. ; Saito, Y. ; Ikebuchi, D. ; Kimura, M. ; Amano, H. ; Nakamura, H. ; Usami, K. ; Namiki, M. ; Kondo, M.
Author_Institution :
Dept. of Inf. & Comput. Sci., Keio Univ., Yokohama, Japan
fYear :
2011
fDate :
12-14 Dec. 2011
Firstpage :
1
Lastpage :
8
Abstract :
A highly energy efficient reconfigurable accelerator called CMA (Cool Mega-Array) is proposed. It consists of a large Processing Element (PE) array without memory elements for maintain result of ALU and configuration data, a small simple programmable micro controller for data management, and the data memory. Unlike traditional coarse grained reconfigurable processors, the power consumption for hardware context switching, storing intermediate data in registers, and clock distribution for them are eliminated from PE array which occupies large area of a chip. Configuration registers are collected to small area of micro controller. The data flow graph mapped on the PE array is static during execution. Various application programs can be implemented by making the best use of flexible data management instructions with the micro controller. When the delay time in the PE array is longer than the data handling time with the micro controller, the supply voltage for the PE array is scaled to reduce the power consumption without degrading the performance. In the opposite case, wave pipelining is applied to enhance PE array performance. A prototype chip CMA-1 with 8 × 8 PE array with 24-bit data width was fabricated in 2.1 × 4.2mm2 65-nm CMOS technology, and achieves 2.4-GOPS/11.2-mW sustained performance. This energy efficiency is comparable to that of the most energy efficient accelerators that have been reported.
Keywords :
CMOS digital integrated circuits; data flow graphs; data handling; low-power electronics; microcontrollers; parallel architectures; pipeline processing; power aware computing; programmable logic arrays; reconfigurable architectures; ALU; CMOS technology; Cool Mega-Array; clock distribution; coarse grained reconfigurable processors; data flow graph; data handling; data memory; energy efficient reconfigurable accelerator; flexible data management; hardware context switching; memory elements; power consumption; processing element array; programmable microcontroller; prototype chip; size 65 nm; supply voltage; wave pipelining; word length 24 bit; Arrays; Clocks; Context; Delay; Leakage current; Registers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field-Programmable Technology (FPT), 2011 International Conference on
Conference_Location :
New Delhi
Print_ISBN :
978-1-4577-1741-3
Type :
conf
DOI :
10.1109/FPT.2011.6132668
Filename :
6132668
Link To Document :
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