Title :
Chip on tape qualification and reliability
Author :
Wang, Tsing-Chow ; Long, Jon ; Kwong, Peter
Author_Institution :
VLSI Technology Inc., San Jose, CA, USA
Abstract :
High-density and high-leadcount chip on tape (COT) technology is emerging as an attractive component for high-performance multichip module applications. A hermetic sealed semiconductor die with gold bump terminations over SiO2 and Si3N4 passivations was bonded to a gold-plated copper tape, using a thermal compression gang bonding technique. The device was subsequently encapsulated and marked. The authors first review the bump design rules, bump characteristics, and the inner lead bond process. The reliability test results of COT devices are presented
Keywords :
hybrid integrated circuits; modules; packaging; reliability; tape automated bonding; COT; MCM; Si3N4 passivations; SiO2 passivations; bump characteristics; bump design rules; chip-on-tape qualification; hermetic sealed semiconductor die; high density chip; high-leadcount chip; inner lead bond process; multichip modules; reliability; reliability test results; thermal compression gang bonding; Bonding processes; Gold; Mechanical factors; Passivation; Qualifications; Semiconductor device packaging; Stress; Testing; Wafer bonding; Wire;
Conference_Titel :
Multi-Chip Module Conference, 1992. MCMC-92, Proceedings 1992 IEEE
Conference_Location :
Santa Cruz, CA
Print_ISBN :
0-8186-2725-5
DOI :
10.1109/MCMC.1992.201450
