A framework for verifying functional correctness in Odin II

Author

Libby, Joseph C. ; Furrow, Ashley ; O´Brien, Paddy ; Kent, Kenneth B.

Author_Institution

Fac. of Comput. Sci., Univ. of New Brunswick, Fredericton, NB, Canada

fYear

2011

fDate

12-14 Dec. 2011

Firstpage

1

Lastpage

6

Abstract

FPGA architecture exploration is a topic of great interest to hardware researchers. By synthesizing many hardware descriptions with different architecture specifications, it is possible to compare the generated circuits and draw a conclusion about those specifications. In order to be confident in results obtained from this exploration, it is necessary to verify that the circuits have been compiled correctly. In this paper, we outline the simulator implemented in the VTR CAD tool flow. We detail the features of the simulator and cover its value to researchers performing architecture exploration.

Keywords

CAD; field programmable gate arrays; FPGA architecture; Odin II; VTR CAD tool flow; architecture specification; functional correctness verification; hardware researcher; Benchmark testing; Field programmable gate arrays; Hardware design languages; Integrated circuit modeling; Pins; Solid modeling; Vectors; Field Programmable Gate Array; circuit simulation; verification; verilog synthesis;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Technology (FPT), 2011 International Conference on

Conference_Location

New Delhi

Print_ISBN

978-1-4577-1741-3

Type

conf

DOI

10.1109/FPT.2011.6132671

Filename

6132671