• DocumentCode
    3052752
  • Title

    Obtaining high fault coverage with circular BIST via state skipping

  • Author

    Touba, Nur A.

  • Author_Institution
    Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
  • fYear
    1997
  • fDate
    27 Apr-1 May 1997
  • Firstpage
    410
  • Lastpage
    415
  • Abstract
    Despite all of the advantages that circular BIST offers compared to conventional BIST approaches in terms of low area overhead, simple control logic, and easy insertion, it has seen limited use because it does not reliably provide high fault coverage. This paper presents a systematic approach for achieving high fault coverage with circular BIST. The basic idea is to add a small amount of logic that causes the circular chain to skip to particular states. This “state skipping” logic can be used to break out of limit cycles, break correlations in the test patterns, and jump to states that detect random-pattern resistant faults. The state skipping logic is added in the chain interconnect and not in the functional logic, so no delay is added to system paths. Result indicate that in many cases, this approach can boost the fault coverage of circular BIST to match that of conventional parallel BIST approaches while still maintaining a significant advantage in terms of hardware overhead and control complexity
  • Keywords
    built-in self test; area overhead; circular BIST; control logic; fault coverage; insertion; limit cycle; random-pattern resistant faults; state skipping; test pattern correlations; Built-in self-test; Circuit faults; Circuit testing; Clocks; Compaction; Flip-flops; Integrated circuit interconnections; Logic testing; Pattern analysis; Test pattern generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium, 1997., 15th IEEE
  • Conference_Location
    Monterey, CA
  • ISSN
    1093-0167
  • Print_ISBN
    0-8186-7810-0
  • Type

    conf

  • DOI
    10.1109/VTEST.1997.600320
  • Filename
    600320