• DocumentCode
    3052928
  • Title

    Accelerated FPGA architecture design: Capabilities and limitations of analytical models

  • Author

    Das, Joydip ; Wilton, Steven J E

  • Author_Institution
    Electr. & Comput. Eng., Univ. of British Columbia, Vancouver, BC, Canada
  • fYear
    2011
  • fDate
    12-14 Dec. 2011
  • Firstpage
    1
  • Lastpage
    8
  • Abstract
    FPGA architects typically use experimental techniques to design new architectures. These techniques are time consuming, thus limiting the number of the architectures that can be investigated. Some previous works use analytical models to significantly accelerate the design of a new architecture. To properly capitalize on the benefits of the analytical models, the designers need to have an understanding of the capabilities and the limitations of the analytical models. In this paper, we use two representative architecture questions to provide such understanding. These two questions respectively investigate the optimization of a general-purpose FPGA architecture and the optimization of an application-specific FPGA architecture. For an optimized general purpose architecture, we show that the conclusions made by the analytical models are similar to the experimental techniques, with respect to three different design goals: area, delay and area-delay trade-off. This justifies the use of the analytical models in optimizing general-purpose FPGA architectures. We also find that the analytical models can not capture the behavior of `some´ applications that contain `discrete effects´. We present this later finding and the related explanations to show that the analytical models can not optimize application-specific architectures in some cases.
  • Keywords
    application specific integrated circuits; field programmable gate arrays; accelerated FPGA architecture design; analytical models; application-specific FPGA architecture; general-purpose FPGA architecture optimization; Analytical models; Computer architecture; Delay; Equations; Field programmable gate arrays; Mathematical model; Solid modeling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Field-Programmable Technology (FPT), 2011 International Conference on
  • Conference_Location
    New Delhi
  • Print_ISBN
    978-1-4577-1741-3
  • Type

    conf

  • DOI
    10.1109/FPT.2011.6132684
  • Filename
    6132684