Performance modeling of a cache system with three interconnect technologies: cyanate ester PCB, chip-on-board and Cu/PI MCM

To understand the tradeoffs in different interconnect technologies, and to investigate the applicability of MCM (multi-chip module) technology to high performance computer products, an electrical performance modeling study on a cache system using three interconnect technologies was conducted. The three technologies were a high density cyanate ester PCB; chip-on-board; and a copper/polyimide MCM with high-density connectors. Placements and layouts for the cache system, using three interconnect technologies, have been done. Active buffer models and interconnect models have been developed. The performance modeling results, including the interconnect, input/output buffers, critical path delays, and the signal integrity assessment, are presented