Title :
Test pattern selection to optimize delay test quality with a limited size of test set
Author :
Inoue, Michiko ; Taketani, Akira ; Yoneda, Tomokazu ; Iwata, Hiroshi ; Fujiwara, Hideo
Author_Institution :
Grad. Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Nara, Japan
Abstract :
Timing-aware ATPGs are being developed to detect small delay faults for high defect coverage for current nanometer VLSI design. However, it results in a large test set compared with test generation targeting traditional fault models. This paper proposes a method to get a limited size of test set with high delay test quality based on statistical delay quality level (SDQL).
Keywords :
VLSI; integrated circuit testing; current nanometer VLSI design; fault model; high delay test quality; statistical delay quality level; test generation; test pattern selection; test set; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Delay; Design automation; Design optimization; Fault detection; System testing; Test pattern generators;
Conference_Titel :
Test Symposium (ETS), 2010 15th IEEE European
Conference_Location :
Praha
Print_ISBN :
978-1-4244-5834-9
Electronic_ISBN :
1530-1877
DOI :
10.1109/ETSYM.2010.5512733
