DocumentCode
3053229
Title
Test pattern selection to optimize delay test quality with a limited size of test set
Author
Inoue, Michiko ; Taketani, Akira ; Yoneda, Tomokazu ; Iwata, Hiroshi ; Fujiwara, Hideo
Author_Institution
Grad. Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Nara, Japan
fYear
2010
fDate
24-28 May 2010
Firstpage
260
Lastpage
260
Abstract
Timing-aware ATPGs are being developed to detect small delay faults for high defect coverage for current nanometer VLSI design. However, it results in a large test set compared with test generation targeting traditional fault models. This paper proposes a method to get a limited size of test set with high delay test quality based on statistical delay quality level (SDQL).
Keywords
VLSI; integrated circuit testing; current nanometer VLSI design; fault model; high delay test quality; statistical delay quality level; test generation; test pattern selection; test set; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Delay; Design automation; Design optimization; Fault detection; System testing; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium (ETS), 2010 15th IEEE European
Conference_Location
Praha
ISSN
1530-1877
Print_ISBN
978-1-4244-5834-9
Electronic_ISBN
1530-1877
Type
conf
DOI
10.1109/ETSYM.2010.5512733
Filename
5512733
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