DocumentCode :
3053269
Title :
Configurable fault-tolerant link for inter-die communication in 3D on-chip networks
Author :
Pasca, Vladimir ; Anghel, Lorena ; Rusu, Claudia ; Benabdenbi, Mounir
Author_Institution :
TIMA Lab., Grenoble, France
fYear :
2010
fDate :
24-28 May 2010
Firstpage :
258
Lastpage :
258
Abstract :
In this paper configurable fault tolerant links are proposed for inter-die communication in stacked 3D SoCs. For high TSV fault rates, links degrade their performance by serial data transmission and signal remapping on the defect free wires. The link degradation is limited to a predetermined value, above which the link is considered non-functional.
Keywords :
fault tolerance; system-on-chip; three-dimensional integrated circuits; 3D on-chip networks; TSV fault rates; configurable fault-tolerant link; defect free wires; inter-die communication; link degradation; serial data transmission; signal remapping; stacked 3D SoC; Circuit faults; Clocks; Counting circuits; Degradation; Fault tolerance; Integrated circuit interconnections; Manufacturing processes; Network-on-a-chip; Switches; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium (ETS), 2010 15th IEEE European
Conference_Location :
Praha
ISSN :
1530-1877
Print_ISBN :
978-1-4244-5834-9
Electronic_ISBN :
1530-1877
Type :
conf
DOI :
10.1109/ETSYM.2010.5512735
Filename :
5512735
Link To Document :
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