Title :
RT level power analysis
Author :
Zhu, Jianwen ; Agrawal, Poonam ; Gajski, Daniel D.
Author_Institution :
Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
Abstract :
Elevating power estimation to architectural and behavioral level is essential for design exploration beyond logic level. In contrast with purely statistical approach, an analytical model is presented to estimate the power consumption in datapath and controller for a given RT level design. Experimental result shows that order of magnitude speed-up over low level tools as well as satisfactory accuracy can be achieved. This work can also serve as the basis for behavioral level estimation tool
Keywords :
circuit layout CAD; high level synthesis; logic CAD; RT level power analysis; analytical model; architectural level; behavioral level; behavioral level estimation tool; controller; design exploration; logic level; power estimation; statistical approach; Capacitance; Clocks; Computer science; Energy consumption; Integrated circuit interconnections; Libraries; Power dissipation; Semiconductor device modeling; Statistics; Switching circuits;
Conference_Titel :
Design Automation Conference, 1997. Proceedings of the ASP-DAC '97 Asia and South Pacific
Conference_Location :
Chiba
Print_ISBN :
0-7803-3662-3
DOI :
10.1109/ASPDAC.1997.600323
