A reconfigurable macro-pipelined systolic accelerator architecture

In this paper, we propose a reconfigurable macro-pipelined systolic architecture (MAPS), which aims to accelerate multiply-accumulate based algorithms by exploiting the temporal parallelism. To illustrate the performance, we implement a 32-PE accelerator on the Xilinx ML605 experiment board for the matrix multiplication and get a peak performance of 51.2 GFLOPS (about 8.0 GFLOPS per PE per GHz). To demonstrate the generality for different algorithms, the 2-dimensional convolution is also implemented on the MAPS. Moreover, the proposed MAPS architecture has the excellent scalability, which is able to scale up to hundreds of GFLOPS using multiple FPGA devices.