Timing speculation in FPGAs: Probabilistic inference of data dependent failure rates

The goal of this work is to model and predict timing failure rates of digital blocks in FPGAs due to delay variation. The timing failures are modelled as transient faults depending on the input vectors to the block, as opposed to conventional critical path failures. Firstly, we present transition tables derived from the truth tables of the logic gates which are apt for our purpose. Next we present a model of transient circuit behaviour based on Bayesian Networks and a method to infer timing failure rates. We implemented these methods with the Bayes Network Toolbox in MATLAB, and compared our results with Monte-Carlo simulations based on SAE-J2748 package for VHDL, and actual implementations and measurements on a Cyclone III FPGA. The test cases are simple arithmetic circuits, such as adders and multipliers. We show that, with this method comparison of error rates is possible among various implementations. We conclude with emphasis on the need for such a method for advancing probabilistic computing paradigms.