High Speed I/O Design Optimization in FCMMAP Packaging

Author

Lee, Chee Hoo ; Lee, Eu Soon ; Victor, Prokofiev ; Udy, Shrivastava A. ; Anne, Augustine E.

Author_Institution

Intel Corp., Penang

fYear

2007

fDate

8-10 Nov. 2007

Firstpage

87

Lastpage

92

Abstract

This paper presents the design optimization work and its implementation in Intel´s High Speed Telecommunication and Optical products in the Flip-Chip Molded-Matrix Array Package (FCMMAP) packaging. The overall high speed modeling methodologies will be explained in this paper to describe electrical analysis work needed to identify the optimizations in the design. Specific substrate design attributes such as impedance matching, discontinuity and material losses will be presented. Validation results based on Intel´s first high speed 40 Gbps prototype will be published in this paper as well.

Keywords

chip scale packaging; integrated circuit design; integrated circuit interconnections; FCMMAP packaging; bit rate 40 Gbit/s; discontinuity; electrical analysis; flip-chip molded-matrix array package; impedance matching; material losses; substrate design; Design optimization; Electromagnetic modeling; Integrated circuit interconnections; Optical arrays; Packaging; Power transmission lines; Prototypes; Pulp manufacturing; Signal design; System performance;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics Manufacturing and Technology, 31st International Conference on

Conference_Location

Petaling Jaya

ISSN

1089-8190

Print_ISBN

978-1-4244-0730-9

Electronic_ISBN

1089-8190

Type

conf

DOI

10.1109/IEMT.2006.4456438

Filename

4456438