Progress in modeling of SMT “stress memorization technique” and prediction of stress enhancement by a novel PMOS SMT process

In this paper, we report progress in the modeling of stress memorization technique (SMT). We show that source/drain deformation plays a critical role in providing enhanced channel stress during SMT process. Stress enhancement as a function of the distance to gate edge of the amorphized source/drain regions is studied. We also propose a novel PMOS SMT process and demonstrate in simulation significant drive current gain additive to that of embedded SiGe process.