Partial reconfiguration logic synthesis by temporal slicing

Partial reconfiguration technology of programmable devices, such as FPGA, enables the virtualization of hardware circuit by temporal multiplexing of active parts (logic slices). An immediate consequence of virtualization is the increase in cardinality of the don´t care set associated with a logic slice. In this paper, we present a logic slicing methodology that exploits the enhanced don´t care set to optimize the hardware circuit for reduction in area. We show that reduced area dynamic reconfigurable slices can be generated for combinational circuits with minimal effect on the critical path. The results reported for MCNC logic synthesis benchmark circuits show an average 40% reduction in area for logic slices.