DocumentCode
3053736
Title
An efficient frame memory interface of MPEG-2 video encoder ASIC chip
Author
Kyeounsoo Kim ; Jong-Seog Koh ; Ki-Bum Suh ; Jong-Wha Chong
Author_Institution
Korea Telecom Access Network Lab., Seoul, South Korea
fYear
1999
fDate
22-24 June 1999
Firstpage
58
Lastpage
59
Abstract
In this paper an efficient frame memory interface of an MPEG-2 video encoder is presented. The proposed architecture takes about 58% less hardware area than the existing architecture (Kim et al. 1997), and results in reducing the total hardware area of the video encoder up to 24.3%.
Keywords
application specific integrated circuits; digital signal processing chips; integrated circuit layout; memory architecture; video coding; MPEG-2 video encoder ASIC chip; architecture; efficient frame memory interface; hardware area; Application specific integrated circuits; Buffer storage; Clocks; Hardware; Logic; Random access memory; Routing; SDRAM; Timing; Video sharing;
fLanguage
English
Publisher
ieee
Conference_Titel
Consumer Electronics, 1999. ICCE. International Conference on
Conference_Location
Los Angeles, CA, USA
Print_ISBN
0-7803-5123-1
Type
conf
DOI
10.1109/ICCE.1999.785167
Filename
785167
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