Title :
A cost-efficient and fully-pipelinable architecture for DCT/IDCT
Author :
Shen-Fu Hsiao ; Wei-Ren Shiue ; Jian-Ming Tseng
Author_Institution :
Inst. of Comput. & Inf. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
Abstract :
A novel low-cost and low-power linear array for computation of discrete cosine transform (DCT) and its inverse is derived from the heterogeneous dependence graph representing the coefficient matrix factorization. The power saving of the architecture is achieved by turning off multipliers whenever the multiplied coefficients are ones.
Keywords :
digital signal processing chips; discrete cosine transforms; matrix decomposition; pipeline processing; transform coding; video coding; DCT/IDCT; coefficient matrix factorization; cost-efficient architecture; discrete cosine transform; fully-pipelinable architecture; heterogeneous dependence graph; inverse discrete cosine transform; linear array; low-cost; low-power; multiplied coefficients; power saving; Arithmetic; Computer architecture; Costs; Discrete cosine transforms; Hardware; Kernel; Matrix decomposition; Multiplexing; Power engineering computing; Read only memory;
Conference_Titel :
Consumer Electronics, 1999. ICCE. International Conference on
Conference_Location :
Los Angeles, CA, USA
Print_ISBN :
0-7803-5123-1
DOI :
10.1109/ICCE.1999.785168
