DocumentCode :
3053763
Title :
Input test data volume reduction based on test vector chains
Author :
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
fYear :
2010
fDate :
24-28 May 2010
Firstpage :
240
Lastpage :
240
Abstract :
The concept of test vector chains was introduced in the context of simulation-based test generation. Test vector chains provide a specific algorithm for performing single-bit changes in order to obtain new test vectors from existing ones. In this algorithm, two test vectors tη and ti2 are used. The test vector chain C(tn,ti2) is obtained by gradually modifying tη into ti2. Starting from tη, each additional test vector in C(tn,ti2) is one bit further from tη and one bit closer to ti2 until ti2 is obtained. It was demonstrated that a test set T has a significant number of test vector chains that are effective in (1) increasing the numbers of detections of faults that were targeted during the generation of Γ; (2) increasing the fault coverage of faults that were not targeted during the generation of Γ; and (3) increasing the fault coverage of target faults when T does not detect all the target faults.
Keywords :
data compression; program testing; vectors; fault coverage; simulation based test generation; single bit changes performance; test vector chains; Circuit faults; Circuit testing; Compaction; Computational modeling; Context modeling; Encoding; Fault detection; Logic testing; Performance evaluation; Test data compression;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium (ETS), 2010 15th IEEE European
Conference_Location :
Praha
ISSN :
1530-1877
Print_ISBN :
978-1-4244-5834-9
Electronic_ISBN :
1530-1877
Type :
conf
DOI :
10.1109/ETSYM.2010.5512753
Filename :
5512753
Link To Document :
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