Analysis and modeling of capacitance-voltage characteristics of poly-Si TFTs using device simulation

Author

Tsuji, Hiroshi ; Kuzuoka, Tsuyoshi ; Kamakura, Yoshinari ; Taniguchi, Kenji

Author_Institution

Div. of Electr., Electron. & Inf. Eng., Osaka Univ., Suita

fYear

2008

fDate

9-11 Sept. 2008

Firstpage

185

Lastpage

188

Abstract

The C-V characteristics of short-channel poly-Si thin-film transistors containing only a single grain boundary (GB) were investigated using a two-dimensional device simulator. It was found that the GB can cause differences in the characteristics of the gate-to-source and gate-to-drain capacitances as a function of the gate voltage, even if no bias is applied between the source and drain. A new equivalent circuit model is proposed to explain the differences in the characteristics due to the GB.

Keywords

equivalent circuits; grain boundaries; silicon; thin film transistors; Si; capacitance-voltage characteristics; device simulation; gate-to-drain capacitances; gate-to-source capacitances; grain boundary; polysilicon TFT; thin-film transistors; two-dimensional device simulator; Analytical models; Capacitance; Capacitance-voltage characteristics; Equivalent circuits; Exponential distribution; Grain boundaries; Information analysis; Probability distribution; Thin film transistors; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Simulation of Semiconductor Processes and Devices, 2008. SISPAD 2008. International Conference on

Conference_Location

Hakone

Print_ISBN

978-1-4244-1753-7

Type

conf

DOI

10.1109/SISPAD.2008.4648268

Filename

4648268